VHDL - Examples

And Gate Example

The VHDL for a two input AND gate is shown below:

library ieee;
use ieee.std_logic_1164.all;

entity and2_gate is
port (
  A,B : in std_logic;
  C: out std_logic
);
end entity;

architecture behave of and2_gate is
begin
  C <= A and B;
end architecture;

Xor Gate Example

The VHDL for a two input Xor gate is shown below:

library ieee;
use ieee.std_logic_1164.all;

entity xor2_gate is
port (
  A,B : in std_logic;
  C: out std_logic
);
end entity;

architecture behave of xor2_gate is
begin
  C <= A xor B;
end architecture;

Half Adder Example

The VHDL for a two input Half Adder is shown below:

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port (
  A,B : in std_logic;
  SUM,CARRY: out std_logic
);
end entity;

architecture behave of half_adder is
begin
  SUM <= A xor B;
  CARRY <= A and B;
end architecture;

Full Adder Example

The VHDL for a two input and carry in Full Adder is shown below:

library ieee;
use ieee.std_logic_1164.all;
 
entity full_adder is
  port (
    A  : in std_logic := '0';
    B  : in std_logic := '0';
    INPUT_CARRY : in std_logic := '0';
    SUM   : out std_logic;
    CARRY : out std_logic
    );
end full_adder;
 
 
architecture rtl of full_adder is
  begin
     SUM   <= A xor B xor INPUT_CARRY;
     CARRY <= ((A xor B) and INPUT_CARRY) or (A and B);
 end rtl;

BCD to 7 Segment Decoder Example

The VHDL for a BCD to 7 Segment Decoder is shown below:

library ieee;
use ieee.std_logic_1164.all;

entity to_7seg_converter is
port (
  BCD_IN : in integer range 0 to 9;
  D_OUT : out std_logic_vector(6 downto 0)
);
end entity;

architecture behave of to_7seg_converter is
begin
  D_OUT <= "1000000" when BCD_IN = 0 else
           "1111001" when BCD_IN = 1 else
           "0100100" when BCD_IN = 2 else
           "0110000" when BCD_IN = 3 else
           "0011001" when BCD_IN = 4 else
           "0010010" when BCD_IN = 5 else
           "0000010" when BCD_IN = 6 else
           "1111000" when BCD_IN = 7 else
           "0000000" when BCD_IN = 8 else
           "0010000" when BCD_IN = 9 else
           "1111111";
end architecture;

Counter

The VHDL for a Counter is shown below:

library ieee;
use ieee.std_logic_1164.all;

entity counter is
port(
  CLK,RST,ENA : in std_logic;
  Q_OUT : out integer range 0 to 128);
end entity;

architecture behave of counter is
  constant COUNT_SIZE : integer := 20;
  signal cnt : integer range 0 to COUNT_SIZE;
begin
  process(CLK,RST)
  begin
    if RST = '1' then
      cnt <= 0;
    elsif rising_edge(CLK) then
      if ENA = '1' then
        if cnt = COUNT_SIZE then
          cnt <= 0;
        else
          cnt <= cnt + 1;
        end if;
      end if;
    end if;
  end process;
  Q_OUT <= cnt;
end architecture;

Multiplexer 4 to 1

The VHDL for a Multiplexer 4 to 1 is shown below:

library ieee;
use ieee.std_logic_1164.all;

entity mux_4to1 is
port (
  D_IN1, D_IN2, D_IN3, D_IN4  : in std_logic_vector(7 downto 0);
  SEL : in std_logic_vector(1 downto 0);
  Q_OUT: out std_logic_vector(7 downto 0)
);
end entity;

architecture behave of mux_4to1 is
begin
  with SEL select
  Q_OUT <= D_IN1 when "00",
           D_IN2 when "01",
           D_IN3 when "10",
           D_IN4 when "11",
           (others=>'Z') when others;
end architecture;

8-Bit Register

The VHDL for a two 8-Bit Register is shown below:

library ieee;
use ieee.std_logic_1164.all;

entity reg_8bit is
  port (
    CLK : in std_logic;
    RST : in std_logic;
    ENA : in std_logic;
    DIN : in std_logic_vector(7 downto 0);
    Q_OUT : out std_logic_vector(7 downto 0));
end entity;

architecture behave of reg_8bit is
begin
  process(CLK,RST)
  begin
    if RST = '1' then
      Q_OUT <= (others=> '0');
    elsif CLK'event and CLK = '1' then
      if ENA = '1' then
        Q_OUT <= DIN;
      else
        Q_OUT <= (others=>'Z');
      end if;
    end if;
  end process;
end architecture;

Clock Divider Example

library ieee;
use ieee.std_logic_1164.all;

entity clk_div is
	generic (
		divider : integer:=5
		);
	port (
		CLK : in std_logic;
		RST: in std_logic;
		STROBE: out std_logic
		);
end clk_div;

architecture clk_div_arc of clk_div is
	begin
  		process(CLK,RST)
  			variable cnt : integer range 0 to divider;
 			begin
    		if RST = '1' then
      			cnt := 0;
    		elsif rising_edge(CLK) then
    			if cnt = divider - 1 then
     				cnt := 0;
     				STROBE <= '1';
    			else
      				cnt := cnt + 1;
      				STROBE <= '0';
    			end if;
    		end if;
  	end process;
end clk_div_arc;

Test Bench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clk_div_tb is
end clk_div_tb;

architecture sim of clk_div_tb is

-- Constants declaration
	constant C_CLK_PRD	: time := 37.037 ns;
	constant C_DEVISOR	: integer := 10;

-- Component declaration
	component clk_div is
	generic(
		divider	: integer := 4
	);
	port (
		CLK		: in    std_logic;
		RST		: in    std_logic;
		
		STROBE	: out   std_logic
	);
	end component;

-- Signals declaration
	signal clk		: std_logic := '0';
	signal rst		: std_logic;
	signal strobe	: std_logic;
	
begin

-- ********************* clock & reset generation ********************
	clk <= not clk after C_CLK_PRD / 2;
	rst <= '1', '0' after 2 us;
-- *******************************************************************

	DUT: clk_div
	generic map (
		divider	=> C_DEVISOR
	)
	port map (
		CLK		=> clk,		
		RST		=> rst,		
		STROBE	=> strobe	
	);
	
end sim;

Single-Port ROM

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Single-Port ROM
entity mem is

	port
	(
        address     : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
        clock       : IN STD_LOGIC  := '1';
        data        : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
        wren        : IN STD_LOGIC ;
        q       : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
	);

end entity;

architecture rtl of mem is

	-- Build a 2-D array type for the ROM
	subtype word_t is std_logic_vector(25 downto 0);
	type memory_t is array(2**11 downto 0) of word_t;

	function init_rom
		return memory_t is
		variable tmp : memory_t := (others => (others => '0'));
	begin
     tmp(0):= "00001000000000000011010000";
     tmp(1):= "00001000000000000010001110";

		return tmp;
	end init_rom;

	signal rom : memory_t := init_rom;

begin
	process(clock)
	begin
	if(rising_edge(clock)) then
		q <= rom(to_integer(unsigned(address)));
	end if;
	end process;

end rtl;

Single port RAM

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Single port RAM with single read/write address 
entity RAM is

  generic 
  (
    DATA_WIDTH : natural := 16;
    ADDR_WIDTH : natural := 8
  );

  port 
  (
    clk   : in std_logic;
    addr  : in std_logic_vector(ADDR_WIDTH-1 downto 0);
    data  : in std_logic_vector((DATA_WIDTH-1) downto 0);
    we    : in std_logic := '1';
    q   : out std_logic_vector((DATA_WIDTH -1) downto 0)
  );

end entity;

architecture rtl of RAM is

  subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;



  signal ram : memory_t := (others => (others => '0'));


begin
  process(clk)
    begin

      if(rising_edge(clk)) then
        if(we = '1') then
          ram(to_integer(unsigned(addr))) <= data;
        end if;
      q <= ram(to_integer(unsigned(addr)));
      end if;
    end process;


end rtl;


Stack Example

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.Numeric_Std.all;

entity stack is
generic (addressBits    :   integer :=8);
    Port ( Clk      : in    std_logic;
           Rst      : in    std_logic:='0';
           Push     : in    std_logic:='0';
           Pop      : in    std_logic:='0';
           Empty    : out   std_logic:='1';
           Full     : out   std_logic:='0';
           Top      : out   std_logic_vector(15 downto 0) := (others=>'0');
           Data     : in    std_logic_vector(15 downto 0));     
end stack;

architecture Behavioral of stack is

signal top_idx      :   integer range 0 to (2**addressBits)-1 :=0;
signal nxt_top_idx  :   integer range 0 to (2**addressBits)-1 :=0;
signal b_Top        :   std_logic_vector(15 downto 0) := (others=>'0');

type bram_type is array(0 to (2**addressBits)-1) of std_logic_vector(15 downto 0);
signal bram : bram_type :=(others=>(others=>'0')) ;

signal  w_ena   :   std_logic   :='0';    
signal  c_ena   :   std_logic   :='0';

type stack_state is (s0, s1, s2);
signal  state       :   stack_state :=  s0;
signal  nxt_state   :   stack_state :=  s0;

begin

process(Clk, Rst) is
begin
    if Rst = '1' then
        state   <=  s0;
        top_idx <=  0;
        Top     <=  (others=>'0');
    elsif rising_edge(Clk) then
        state   <=  nxt_state;
        top_idx <=  nxt_top_idx;
        Top     <=  b_Top;
    end if;  
end process;

process(state , Push, Pop, Data, bram, top_idx, nxt_top_idx) is
begin
    case state is
        when s0 =>  --stack is empty
            Empty           <=  '1';
            Full            <=  '0';
            nxt_top_idx     <=  0;
            if Push = '1' and Pop = '0' then
                nxt_state   <=  s1;
                w_ena       <=  '1';
                c_ena       <=  '0';
                b_Top       <=  Data;
            else
                nxt_state   <=  s0;
                w_ena       <=  '0';
                c_ena       <=  '0';
                b_Top       <=  (others => '0');
            end if;
        when s1 =>  --stack isn't empty nor full
            Empty   <=  '0';
            Full    <=  '0';
            if Push = '0' and Pop = '1' then
                if top_idx = 0 then
                    b_Top       <=  (others=>'0');
                    nxt_top_idx <=  top_idx;
                    nxt_state   <=  s0;
                else
                    b_Top       <=  bram(nxt_top_idx);
                    nxt_top_idx <=  top_idx - 1;
                    nxt_state   <=  s1;
                end if;
                w_ena       <=  '0';
                c_ena       <=  '1';
            elsif Push = '1' and Pop = '0' then
                b_Top       <=  Data;
                nxt_top_idx <=  top_idx + 1;
                if top_idx = (2**10)-2 then
                    nxt_state   <=  s2;
                else
                    nxt_state   <=  s1;
                end if;
                w_ena       <=  '1';
                c_ena       <=  '0';
            else
                b_Top       <=  bram(nxt_top_idx);
                nxt_top_idx <=  top_idx;
                nxt_state   <=  s1;
                w_ena       <=  '0';
                c_ena       <=  '0';
            end if;
        when s2 =>  --stack is full
            Empty   <=  '0';
            Full    <=  '1';
            b_Top   <=  bram(nxt_top_idx);
            if Push = '0' and Pop = '1' then
                nxt_top_idx <=  top_idx - 1;
                nxt_state   <=  s1;
                w_ena       <=  '0';
                c_ena       <=  '1';
            else
                nxt_top_idx <=  top_idx;
                nxt_state   <=  s2;
                w_ena       <=  '0';
                c_ena       <=  '0';
            end if;
        when others =>
            Empty       <=  '0';
            Full        <=  '0';
            b_Top       <=  (others=>'0');
            nxt_top_idx <=  0;
            nxt_state   <=  s0;
            w_ena       <=  '0';
            c_ena       <=  '0';
    end case;
end process;

process(Clk, Rst) is
begin
    if Rst = '1' then
        bram    <=  (others=>(others=>'0'));
    elsif rising_edge(Clk) then
        if w_ena='1' and c_ena ='0' then
            bram(nxt_top_idx)   <=  Data;
        elsif w_ena='0' and c_ena ='1' then
            bram(top_idx)       <=  (others=>'0');
        else
            bram                <=  bram;
        end if;
    end if;  
end process;

end Behavioral;

Test Bench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity stack_tb is
end stack_tb;

architecture Behavioral of stack_tb is

component stack is
    Port ( Clk      : in    std_logic:='0';
           Rst      : in    std_logic:='0';
           Push     : in    std_logic:='0';
           Pop      : in    std_logic:='0';
           Empty    : out   std_logic:='1';
           Full     : out   std_logic:='0';
           Top      : out   std_logic_vector(15 downto 0) := (others=>'0');
           Data     : in    std_logic_vector(15 downto 0));
end component;

signal  Clk      :  std_logic:='0';
signal  Rst      :  std_logic:='0';
signal  Push     :  std_logic:='0';
signal  Pop      :  std_logic:='0';
signal  Empty    :  std_logic:='1';
signal  Full     :  std_logic:='0';
signal  Top      :  std_logic_vector(15 downto 0) := (others=>'0');
signal  Data     :  std_logic_vector(15 downto 0) := (others=>'0');

begin

Clk <=  not Clk after 10 ns ;
Rst <= '0';
Push<= '0' , '1' after 20 ns , '0' after 60 ns , '1' after 100 ns , '0' after 20580 ns;
Pop <= '0' , '1' after 60 ns , '0' after 80 ns , '1' after 120 ns , '0' after 140 ns , '1' after 20580 ns;
Data<= x"00FF" ,x"EEEE" after 40 ns, x"DDDD" after 100 ns , x"EAEA" after 140 ns , X"1234" after 20560 ns;

DUT : stack
port map(
            Clk     =>  Clk,
            Rst     =>  Rst,
            Push    =>  Push,
            Pop     =>  Pop,
            Empty   =>  Empty,
            Full    =>  Full,
            Top     =>  Top,
            Data    =>  Data);


end Behavioral;


Ultrasonic Sensor HC-SR04 Example

library ieee;
use ieee.std_logic_1164.all;

entity sensor_driver is

  generic(
    triger_pulse: integer:= 6; -- assume that every clock is 1ms
    max_pulse_echo: integer:= 500;
    wait_time: integer:= 20;
    -- time = (2*distance/speed)
    -- (2*0.01/343) = 58.3μ
    -- pulses = time/(clock_time)
    -- number of pulses = 58.3μ/0.02μ(50MHZ) = 2915 pulses
    number_of_pulses_per_cm : integer:= 2915
    );
  port( 
    ECHO, RST, SYS_CLK, TRIG_IN :in std_logic;
    EOC, TRIG_OUT: out std_logic;
    DURATION : out integer range 0 to max_pulse_echo);
end entity;

architecture behave of sensor_driver is
  signal cnt_echo : integer range 0 to max_pulse_echo + 1 :=0 ;
  signal cnt : integer range 0 to triger_pulse := 0;
  signal mode : integer range 0 to 4:=0;
  signal start_get_echo : integer range 0 to 1 :=0;
  signal wait_t : integer range 0 to wait_time :=0;
  signal data_in_cm : integer range 0 to max_pulse_echo :=0;
  signal counter_cm_cycles : integer range 0 to number_of_pulses_per_cm + 1 :=0;
  begin
    DURATION <= data_in_cm;
    process(SYS_CLK,RST)
    begin
      if RST = '1' then
       mode <= 0;
       wait_t <= 0;
       start_get_echo <= 0;
       cnt <= 0;
       TRIG_OUT <= '0';
       EOC <= '0';
       cnt_echo <= 0;
       data_in_cm<= 0 ;
       counter_cm_cycles<= 0;
       elsif rising_edge(SYS_CLK) then
         EOC <= '0';
         if TRIG_IN = '1' then
       if mode = 0 then -- sends trig
         if cnt = triger_pulse - 1 then
           TRIG_OUT <= '0';
           cnt <= 0;
           mode <= 1;
           else
           TRIG_OUT <= '1';
           cnt <= cnt + 1;
           cnt_echo <= 0;
           data_in_cm <= 0;
           counter_cm_cycles <= 0;
           start_get_echo <= 0;
         end if;
       elsif mode = 1 then -- waits for echo
        if start_get_echo = 0 then
          if ECHO = '1' then
            cnt_echo <= cnt_echo + 1;
            counter_cm_cycles <=counter_cm_cycles + 1;
            start_get_echo <= 1;
          end if;
          elsif start_get_echo = 1 then
            if ECHO = '1' then
              cnt_echo <= cnt_echo + 1;
              counter_cm_cycles <=counter_cm_cycles + 1;
              if counter_cm_cycles >= number_of_pulses_per_cm - 1 then
                counter_cm_cycles <= 0;
                data_in_cm <= data_in_cm + 1;
              end if;
              if cnt_echo = max_pulse_echo - 1 then
                mode <= 3;
              end if;
              else
              start_get_echo <= 0;
              mode <= 2;
            end if;
          end if;
       elsif mode = 2 then -- waits to send EOC after end of echo
         if wait_t = wait_time - 1 then
           wait_t <= 0;
            mode <= 4; 
           cnt <= 0;
           EOC <= '1';
           else
           wait_t <= wait_t + 1;
         end if;
         
       elsif mode = 3 then -- waits to send EOC after end of echo, when number is 999cm
         if ECHO = '1' then
           else
           if wait_t = wait_time - 1 then
            wait_t <= 0;
            mode <= 4; 
            cnt <= 0;
            EOC <= '1';
            else
            wait_t <= wait_t + 1;
          end if;
        end if;

       elsif mode = 4 then -- end of measurement.
        mode <= 0;
      end if;

    end if;
  end if;
end process;

end architecture;

Test Bench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sensor_driver_tb is
end entity;

architecture behave of sensor_driver_tb is
  
component sensor_driver is
  generic(triger_pulse: integer:= 6; -- assume that every clock is 1ms
  max_pulse_echo: integer:= 500;
  wait_time: integer:= 20);
port( 
  ECHO, RST, SYS_CLK, TRIG_IN :in std_logic;
  EOC, TRIG_OUT: out std_logic;
  DURATION : out integer range 0 to max_pulse_echo);
end component;

-- Constants declaration
  constant C_CLK_PRD  : time := 20 ns; -- F_s = 50Mhz
  constant trig_p: integer := 600; -- what's needed for triger :
  -- 600*20 ns = 12000 ns = 12 us 
  constant max_p_v: integer := 1800000; -- 36 ms / 20 ns =
  -- 36 / 20 * 10^6 = 1800000
  constant w_t: integer :=  2500000; --  2500000*20ns = 50ms
  
-- signals
  
  signal clk    : std_logic := '0';
  signal rst    : std_logic := '0';
  signal echo : std_logic := '0';
  signal trig_in : std_logic := '0';
  signal trig_out : std_logic := '0';
  signal eoc : std_logic;
  signal dur : integer range 0 to max_p_v;
  
begin
-- ********************* clock & reset generation ********************
  clk <= not clk after C_CLK_PRD / 2;
  rst <= '1', '0' after 1 us;
  trig_in <= '0', '1' after 5 us;
  echo <= '0', '1'  after 20 us, '0' after 30 us;
-- *******************************************************************
U1: sensor_driver
  generic map(triger_pulse => trig_p, -- assume that every clock is 1ms
  max_pulse_echo => max_p_v,
  wait_time => w_t)
  port map( 
  ECHO => echo,
  RST => rst,
  SYS_CLK => clk, 
  TRIG_IN => trig_in,
  EOC => eoc,
  TRIG_OUT => trig_out,
  DURATION => dur
  );

end architecture;

Debounce

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY debounce IS
  GENERIC(
    stable_clocks : INTEGER := 10); --clocks for stable input.
  PORT(
    clk     : IN  STD_LOGIC := '0'; 
    reset_n : IN  STD_LOGIC := '1';  
    debounce_input  : IN  STD_LOGIC;  
    stable_output  : OUT STD_LOGIC); 
END debounce;

ARCHITECTURE rtl OF debounce IS
  SIGNAL flipflops   : STD_LOGIC_VECTOR(1 DOWNTO 0);
  SIGNAL counter_set : STD_LOGIC;                 
BEGIN

  counter_set <= flipflops(0) xor flipflops(1);  
  
  PROCESS(clk, reset_n)
    VARIABLE count :  INTEGER RANGE 0 TO stable_clocks; 
  BEGIN
    IF(reset_n = '0') THEN                  
      flipflops(1 DOWNTO 0) <= "00";        
      stable_output <= '0';                               
    ELSIF(clk'EVENT and clk = '1') THEN        
      flipflops(0) <= debounce_input;                       
      flipflops(1) <= flipflops(0);                
      If(counter_set = '1') THEN                     
        count := 0;                                   
      ELSIF(count < stable_clocks) THEN  
        count := count + 1;                      
      ELSE                                    
        stable_output <= flipflops(1);                      
      END IF;    
    END IF;
  END PROCESS;
  
END rtl;

TOP-LEVEL Example

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sec_meter is
port(
  CLK,RST: in std_logic;
  SEC_ONES : out std_logic_vector(6 downto 0);
  SEC_TENS : out std_logic_vector(6 downto 0);
  MIN_ONES : out std_logic_vector(6 downto 0);
  MIN_TENS : out std_logic_vector(6 downto 0)
);
end entity;

architecture behave of sec_meter is

-------------**********-----------------
-------------components-----------------
-------------**********-----------------
component clk_div is
generic (divider : integer:= 27000000);
port(
  CLK,RST: in std_logic;
  STROBE : out std_logic);
end component;

component to_7seg_converter is
port (
  BCD_IN : in integer range 0 to 9;
  D_OUT : out std_logic_vector(6 downto 0)
);
end component;

component counter_2_digits is
generic(COUNT_SIZE : integer:= 10);
port(
  CLK,RST,ENABLE: in std_logic;
  ONES,TENS: out integer range 0 to 9;
  OVERFLOW : out std_logic);
end component;
-------------**********-----------------
-------------signals--------------------
-------------**********-----------------
  signal clk1   : std_logic := '0';
  signal rst1   : std_logic;
  signal ove    : std_logic;
  signal strobe         : std_logic;
        signal enb              : std_logic;
  signal one          : integer range 0 to 9;
        signal ten              : integer range 0 to 9;
  signal one2         : integer range 0 to 9;
        signal ten2             : integer range 0 to 9;
        signal out1             : std_logic_vector(6 downto 0);
        signal out2             : std_logic_vector(6 downto 0);
        signal out3             : std_logic_vector(6 downto 0);
        signal out4             : std_logic_vector(6 downto 0);
        signal dont_con         : std_logic;
-------------**********-----------------
-------------constant-------------------
-------------**********-----------------

  constant C_DEVISOR  : integer := 27000000;
        constant MODULU         : integer := 6;
begin


-------------conections-------------------
clk1 <= CLK;
rst1 <= RST;
SEC_ONES <= out1;
SEC_TENS <= out2;
MIN_ONES <= out3;
MIN_TENS <= out4;
------------------------------------------
S11: clk_div
generic map (divider=> C_DEVISOR)
port map (
   CLK => clk1, 
   RST=> rst1,  
   STROBE => strobe);

S12: counter_2_digits 
generic map(COUNT_SIZE => MODULU )
port map(
  CLK => clk1,
  RST => rst1,
  ENABLE => strobe,
  ONES => one,
  TENS => ten,
  OVERFLOW => ove
);

S13: to_7seg_converter 
port map(
  BCD_IN => one,
  D_OUT => out1
);

S14: to_7seg_converter 
port map(
  BCD_IN => ten,
  D_OUT => out2
);

S22: counter_2_digits 
generic map(COUNT_SIZE => MODULU )
port map(
  CLK => clk1,
  RST => rst1,
  ENABLE => ove,
  ONES => one2,
  TENS => ten2,
   OVERFLOW => dont_con
);

S23: to_7seg_converter 
port map(
  BCD_IN => one2,
  D_OUT => out3
);

S24: to_7seg_converter 
port map(
  BCD_IN => ten2,
  D_OUT => out4
);

end architecture;

Test Bench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sec_meter_tb is
end entity;

architecture behave of sec_meter_tb is
component sec_meter is
port(
  CLK,RST: in std_logic;
  SEC_ONES : out std_logic_vector(6 downto 0);
  SEC_TENS : out std_logic_vector(6 downto 0);
  MIN_ONES : out std_logic_vector(6 downto 0);
  MIN_TENS : out std_logic_vector(6 downto 0)
);
end component;

-- Constants declaration
  constant C_CLK_PRD  : time := 37.037 ns;
-- signals
  
  signal clk    : std_logic := '0';
  signal rst    : std_logic := '0';

        signal sec1             : std_logic_vector(6 downto 0);
        signal sec2             : std_logic_vector(6 downto 0);
        signal min1             : std_logic_vector(6 downto 0);
        signal min2             : std_logic_vector(6 downto 0);
begin
-- ********************* clock & reset generation ********************
  clk <= not clk after C_CLK_PRD / 2;
  rst <= '1', '0' after 1 us;
-- *******************************************************************
U1: sec_meter 
port map(
  CLK => clk,
  RST => rst,
  SEC_ONES => sec1,
  SEC_TENS => sec2,
  MIN_ONES => min1,
  MIN_TENS => min2
);
end architecture;

Parity Generator Example

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY parity_generator IS
  GENERIC(
    word_size    : INTEGER   := 8;    --number of input bits
    even_or_odd : STD_LOGIC := '0'); --'0' for even, '1' for odd parity
  PORT(
    word : IN STD_LOGIC_VECTOR(7 DOWNTO 0):= x"fe"; 
    parity : OUT STD_LOGIC);                 
END parity_generator;

ARCHITECTURE arc OF parity_generator IS
  SIGNAL  parity_calculation : STD_LOGIC_VECTOR(word_size DOWNTO 0);
BEGIN
  parity_calculation(0) <= even_or_odd; 
  generate_parity: FOR i IN 0 to word_size-1 GENERATE
    parity_calculation(i+1) <= parity_calculation(i) XOR word(i); 
  END GENERATE;
  parity <= parity_calculation(word_size);  
  
END arc;