VHDL - Basics

Entity


library ieee;
use ieee.std_logic_1164.all;
entity example is
	generic (
    generic_1 : std_logic
	);
  port (
    input_1    : in  std_logic;
    input_2    : in  std_logic;
    output	   : out std_logic
  );
end entity example;

Architecture

library ieee;
use ieee.std_logic_1164.all;
entity example is
	generic (
    generic_1 : std_logic
	);
  port (
    input_1    : in  std_logic;
    input_2    : in  std_logic;
    output	   : out std_logic
  );
end entity example;

architecture rtl of example is
  signal signal_1 : std_logic;
begin
  signal_1   <= input_1 and generic_1;
  output <= signal_1 or input_2;
end rtl;

Process

library ieee;
use ieee.std_logic_1164.all;
entity example is
	generic (
    generic_1 : std_logic
	);
  port (
    input_1    : in  std_logic;
    input_2    : in  std_logic;
    output	   : out std_logic
  );
end entity example;

architecture rtl of example is
  signal signal_1 : std_logic;
begin
  
  process (input_1, input_2)
    begin
      signal_1   <= input_1 and generic_1;
      output <= signal_1 or input_2;
    end process;
end rtl;

Operators

Logical Operators

Operator Description
and And Gate
or Or Gate
nand Nand Gate
nor Nor Gate
xor Xor Gate
not Not Gate

Relational Operators

Operator Description
= Equal to
/= Not equal to
> Greater than
< Less than
>= Greater than or equal to
<= Less than or equal to

Arithmetic Operators

Operator Description
+ Addition
- Subtraction
* Multiplication
/ Division
mod Modulus
rem Remainder
abs Absolute Value
** Exponentiation

Shift Operators

Operator Description
sll Shift Left Logical
srl Shift Right Logical
sla Shift Left Arithmetic
sra Shift Right Arithmetic
rol Rotate Left Logical
ror Rotate Right Logical

Conditions

If Statement

library ieee;
use ieee.std_logic_1164.all;
entity example is
  port (
    input_1    : in  std_logic_vector(2 downto 0):= "011";
    output	   : out std_logic_vector(2 downto 0)
  );
end entity example;

architecture rtl of example is
begin
  
  process (input_1)
    begin
      if input_1 = "001" then 
        output <= "011";
      elsif input_1 = "011" then
        output <= "001";  
      else     
        output <= "111";
      end if;
    end process;
end rtl;
		

Case Statement

case input_1 is
  when "000" | "100" =>
    output <= "000";
  when "001" =>
    output <= "001";
  when "010" =>
    output <= "010";
  when others =>
    output <= "111";
end case;
		

Example


library ieee;
use ieee.std_logic_1164.all;
entity example is
  port (
    input_1    : in  std_logic_vector(2 downto 0):= "011";
    output	   : out std_logic_vector(2 downto 0)
  );
end entity example;

architecture rtl of example is
begin
  
  process (input_1)
    begin
      case input_1 is
        when "000" | "100" =>
          output <= "000";
        when "001" =>
          output <= "001";
        when "010" =>
          output <= "010";
        when others =>
          output <= "111";
      end case;
    end process;
end rtl;

Functions

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity example is
  port (
    input_1    : in  std_logic_vector(2 downto 0):= "011";
    input_2    : in  std_logic_vector(2 downto 0):= "011";
    output	   : out std_logic_vector(2 downto 0)
  );
end entity example;

architecture rtl of example is
  function addition (
                      a : in std_logic_vector(2 downto 0);
                      b : in std_logic_vector(2 downto 0)
                    )
  return std_logic_vector is
    variable sum_result : std_logic_vector(2 downto 0);
    begin
      sum_result := std_logic_vector(unsigned(a) + unsigned(b));
      return sum_result;
  end function addition;
begin
 
  process (input_1, input_2)
    begin
        output <= addition(input_1,input_2);
    end process;
end rtl;