library ieee;
use ieee.std_logic_1164.all;
entity derivative_down is
port ( CLK, D_IN : in std_logic;
STROBE : out std_logic);
end entity;
architecture behave of derivative_down is
signal SAMP1_D_IN, NOT_SAMP1_D_IN : std_logic;
begin
STROBE <= NOT_SAMP1_D_IN AND SAMP1_D_IN;
process(CLK)
begin
if CLK'EVENT and CLK = '1' then
SAMP1_D_IN <= not D_IN;
NOT_SAMP1_D_IN <= not SAMP1_D_IN;
end if;
end process;
end architecture;