Stabilizer in vhdl example

procedure stabilizer (signal CLK, TAKE_SIG, RST : in std_logic;
	signal PUT_OUT : out std_logic;
	signal INSIDE_WIRE  : inout std_logic) is

begin

	if RST = '1' then
		INSIDE_WIRE <= '0';
		PUT_OUT <= '0';
		elsif rising_edge(CLK) then
			INSIDE_WIRE <= TAKE_SIG;
			PUT_OUT <= INSIDE_WIRE;
		end if;
	end procedure;