And gate program in vhdl

And gate code:

library ieee;
use ieee.std_logic_1164.all;

entity and2_gate is
port (
  A,B : in std_logic;
  C: out std_logic
);
end entity;

architecture behave of and2_gate is
begin
  C <= A and B;
end architecture;

Do file for and gate:

restart -f
force A 0 0,1 100,0 200,1 300
force B 0 0,0 100,1 200,1 300
run 500