Shift register vhdl code

library ieee;
use ieee.std_logic_1164.all;

entity shift_reg is
generic (
    N       : integer := 4
);
port (
    CLK     : in    std_logic;
    RST     : in    std_logic;
    ENA     : in    std_logic;
    L_R     : in    std_logic;
    Q       : out   std_logic_vector(N-1 downto 0)
);
end entity;

architecture behave of shift_reg is

    signal shift_register   : std_logic_vector(N-1 downto 0);

begin

    shift_reg_process: process(CLK, RST)
    begin
        if RST = '1' then
            shift_register <= (0=>'1', others=>'0');
        elsif rising_edge(CLK) then
            if ENA = '1' then
                if L_R = '0' then
                    shift_register(N-1 downto 1) <= shift_register(N-2 downto 0);
                    shift_register(0) <= shift_register(N-1);
                else
                    shift_register(N-2 downto 0) <= shift_register(N-1 downto 1);
                    shift_register(N-1) <= shift_register(0);
                end if;
            end if; 
        end if;
    end process;

    Q <= shift_register;

end architecture;