Bcd to 7 segment function in vhdl

function To_7Seg (BCD_IN:integer range 0 to 9) return std_logic_vector is
variable D_OUT: std_logic_vector (6 downto 0) := (others=>'0');
begin
  case BCD_IN is
  when 0       =>  D_OUT := "1000000";
  when 1       =>  D_OUT := "1111001";
  when 2       =>  D_OUT := "0100100";
  when 3       =>  D_OUT := "0110000";
  when 4       =>  D_OUT := "0011001";
  when 5       =>  D_OUT := "0010010";
  when 6       =>  D_OUT := "0000010";
  when 7       =>  D_OUT := "1111000";
  when 8       =>  D_OUT := "0000000";
  when 9       =>  D_OUT := "0010000";
  when others  =>  D_OUT := "1111111";
end case;
return D_OUT;
end function;