Counter in vhdl

library ieee;
use ieee.std_logic_1164.all;

entity counter is
port(
  CLK,RST,ENA : in std_logic;
  Q_OUT : out integer range 0 to 128);
end entity;

architecture behave of counter is
  constant COUNT_SIZE : integer := 20;
  signal cnt : integer range 0 to COUNT_SIZE;
begin
  process(CLK,RST)
  begin
    if RST = '1' then
      cnt <= 0;
    elsif rising_edge(CLK) then
      if ENA = '1' then
        if cnt = COUNT_SIZE then
          cnt <= 0;
        else
          cnt <= cnt + 1;
        end if;
      end if;
    end if;
  end process;
  Q_OUT <= cnt;
end architecture;