Derivative down in vhdl

library ieee;
use ieee.std_logic_1164.all;

entity derivative_down is
  port ( CLK, D_IN : in std_logic;
    STROBE : out std_logic);
end entity;

architecture behave of derivative_down is
  signal SAMP1_D_IN, NOT_SAMP1_D_IN : std_logic;
begin
  STROBE <= NOT_SAMP1_D_IN AND SAMP1_D_IN;
  process(CLK)
  begin
    if CLK'EVENT and CLK = '1' then
      SAMP1_D_IN <= not D_IN;
      NOT_SAMP1_D_IN <= not SAMP1_D_IN; 
    end if;
  end process;
end architecture;

TB:

library ieee;
use ieee.std_logic_1164.all;

entity derivative_down_tb is
end entity;

architecture behave of derivative_down_tb is

component derivative_down is
  port ( CLK, D_IN : in std_logic;
    STROBE : out std_logic);
end component;
-- Constants declaration
        constant C_CLK_PRD	: time := 20 ns; -- F_s = 50Mhz
-- signals
  
	signal clk		: std_logic := '0';
	signal rst		: std_logic := '0';
        signal din              : std_logic := '0';
        signal strobe           : std_logic := '0';
begin
	-- ********************* clock & reset generation ********************
	clk <= not clk after C_CLK_PRD / 2;
	rst <= '1', '0' after 1 us;
        din <= '0', '1' after 2 us, '0' after 3 us;


	U1: derivative_down 
 	 port map( CLK => clk, D_IN => din,
    	STROBE => strobe);
	

        

end architecture;