Vhdl top level example

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use work.my_pace.all;
use ieee.std_logic_arith.all;
entity distance_measure_sys is
  	generic(
		 C_NUMBER_OF_PULSES_PER_CM : integer:= 2915; 
		 C_PULSE_WIDTH: integer:= 600; -- 600 = 12־¼ in 50MHZ clock.  
		 C_WAIT_TIME: integer:= 2500000; -- 2500000 = 50m in 50MHZ clock.  
		 C_MAX_PULSE_ECHO: integer:= 1800000;  -- 1800000 = 36m in 50MHZ clock.
		 C_CLOCK_DIVIDER : integer:= 5209; --
		 C_PARITY_ENABLE : std_logic:= '0'; -- parity_enable = '0' no parity
		 C_EXTRE_STOP_BIT_ENABLE : std_logic:= '0' -- EXTRE_STOP_BIT_ENABLE = '1' use two stop bit.
    );
	port(
		CLK_SYS,RST,START_MEASURE,ECHO: in std_logic;
		TRIG_OUT,Tx_UART_OUT: out std_logic;
		-- display in cm
		LED: out std_logic;
		LED2: out std_logic;
		LED3: out std_logic;
  		ONES : out std_logic_vector(6 downto 0);
  		TENS : out std_logic_vector(6 downto 0);
 		HUNDS : out std_logic_vector(6 downto 0)

  );
end entity;

architecture behave of distance_measure_sys is


-------------components-----------------
component bin2bcd_12bit_sync is
port ( 
    binIN       : in    STD_LOGIC_VECTOR (11 downto 0);     -- this is the binary number
    ones        : out   STD_LOGIC_VECTOR (3 downto 0);      -- this is the unity digit
    tenths      : out   STD_LOGIC_VECTOR (3 downto 0);      -- this is the tens digit
    hunderths   : out   STD_LOGIC_VECTOR (3 downto 0);      -- this is the hundreds digit
    thousands   : out   STD_LOGIC_VECTOR (3 downto 0);      -- 
    clk         : in    STD_LOGIC                           -- clock input
);
end component;


component uart_driver is
  -- parity_enable = '0' no parity , EXTRE_STOP_BIT_ENABLE = '1' use two stop bit 1.
  generic (
    clock_divider: integer:= 10;
    parity_enable: std_logic:= '0';
    extre_stop_bit_enable:std_logic := '0');
  port(
    CLK_SYS,RST,SEND_DATA_TRIGGER: in std_logic;
    Tx_DATA_OUTPUT: out std_logic := '1';-- Tx => Transmit
    READY_TO_SEND_DATA: out std_logic := '0'; 
    DATA_IN: in std_logic_vector(3 downto 0) := "0000"
    );
end component;



component send_data_controller is
port(
  CLK_SYS,RST,DATA_IN_VALID,READY_TO_SEND_DATA: in std_logic;
  ONES, TENTHS , HUNDERTHS : in   STD_LOGIC_VECTOR (3 downto 0);      -- this is the unity digit
  DATA_OUT : out std_logic_vector(3 downto 0) := "0000";
  SEND_DATA_TRIGGER,SEND_DATA_IN_UART_FLAG: out std_logic := '0'
  );
end component;



component logic is
port(
	SYS_CLK,RST,DATA_IN_VALID,START_MEASURE,SEND_DATA_IN_UART_FLAG: in std_logic;
	DATA_IN : in integer;
	SEND_TRIGGER : out std_logic;
  CM: out integer range 0 to 999 -- output in cm
  );
end component;

component to_7seg_converter is
port (
	BCD_IN : in std_logic_vector (3 downto 0);
	D_OUT : out std_logic_vector(6 downto 0)
	);
end component;

component sensor_driver is
  generic(
  	triger_pulse: integer:= 6; 
  	max_pulse_echo: integer:= 2500000;
  	wait_time: integer:= 20;
  	number_of_pulses_per_cm : integer:= 2915); -- defult for 50MHZ clock and sound_speed = 343 m / s 

  port( 
  	ECHO, RST, SYS_CLK, TRIG_IN :in std_logic;
  	EOC, TRIG_OUT: out std_logic;
  	DURATION : out integer range 0 to max_pulse_echo);
end component;

component derivative_down is
  port ( CLK, D_IN : in std_logic;
    STROBE : out std_logic);
end component;
-------------signals--------------------
signal led1 : std_logic :='0';

signal s_clk_sys, s_rst,eoc,s_start_measure, trigger, s_echo , 
s_trig_out : std_logic := '0';
signal data_in : integer :=0;
signal ones_in, tens_in, hunds_in : std_logic_vector(3 downto 0);
signal ones_out, tens_out, hunds_out : std_logic_vector(6 downto 0);
signal dont_con : std_logic_vector (3 downto 0); 
signal put_out : integer range 0 to 999;
signal fixed_put_out: std_logic_vector (11 downto 0); 
signal RAW_ECHO, RAW_START_MEASURE,strobe : std_logic;
signal READY_ECHO, READY_START_MEASURE : std_logic;
signal s_send_data_controller_data_out: std_logic_vector(3 downto 0);
signal s_uart_driver_READY_TO_SEND_DATA: std_logic;
signal s_send_data_controller_SEND_DATA_TRIGGER, s_send_data_controller_READY_TO_SEND_DATA: std_logic := '0';
signal S_Tx_UART_OUT,s_send_data_in_uart_flag: std_logic;
-------------constant-------------------

--constant C_NUMBER_OF_PULSES_PER_CM : integer:= 2915; 
--constant C_PULSE_WIDTH: integer:= 600; -- 600 = 12־¼ in 50MHZ clock.  
--constant C_WAIT_TIME: integer:= 2500000; -- 2500000 = 50m in 50MHZ clock.  
--constant C_MAX_PULSE_ECHO: integer:= 1800000;  -- 1800000 = 36m in 50MHZ clock.

--constant C_CLOCK_DIVIDER : integer:= 5209; 
--constant C_PARITY_ENABLE : std_logic:= '0'; -- parity_enable = '0' no parity
--constant C_EXTRE_STOP_BIT_ENABLE : std_logic:= '0'; -- EXTRE_STOP_BIT_ENABLE = '1' use two stop bit.




begin
-------------conections-----------------

process(CLK_SYS,RST)
begin
if RST = '1' then
LED <= '0';
LED2 <= '0';
LED3 <= '0';
elsif rising_edge(CLK_SYS) then
if trigger = '1' then
LED <= '1';
end if;
if s_trig_out = '1' then
LED2 <= '1';
end if;
if ECHO = '1' then
LED3 <= '1';
end if;
end if;
end process;



stabilizer (CLK => s_clk_sys , TAKE_SIG => START_MEASURE, 
RST => s_rst ,PUT_OUT => READY_START_MEASURE , 
INSIDE_WIRE => RAW_START_MEASURE);

stabilizer (CLK => s_clk_sys, TAKE_SIG => ECHO , 
RST => s_rst ,PUT_OUT => READY_ECHO, INSIDE_WIRE => RAW_ECHO);

fixed_put_out <= conv_std_logic_vector(put_out, 12);
s_clk_sys <= CLK_SYS;
s_rst <= RST;
s_start_measure <= READY_START_MEASURE;
s_echo <= READY_ECHO;
TRIG_OUT <= s_trig_out;
ONES <= ones_out;
TENS <= tens_out;
HUNDS <= hunds_out;
Tx_UART_OUT <= S_Tx_UART_OUT;


U6: uart_driver
  -- parity_enable = '0' no parity , EXTRE_STOP_BIT_ENABLE = '1' use two stop bit 1.
generic map (
	clock_divider => C_CLOCK_DIVIDER,
	parity_enable => C_PARITY_ENABLE,
	extre_stop_bit_enable =>  C_EXTRE_STOP_BIT_ENABLE
	)
port map(
	CLK_SYS => s_clk_sys,
	RST =>  s_rst,
	SEND_DATA_TRIGGER =>  s_send_data_controller_SEND_DATA_TRIGGER,
	Tx_DATA_OUTPUT =>  S_Tx_UART_OUT,
	READY_TO_SEND_DATA =>  s_send_data_controller_READY_TO_SEND_DATA,
	DATA_IN =>  s_send_data_controller_data_out
);

U7: send_data_controller
port map(
  CLK_SYS => s_clk_sys,
  RST => s_rst,
  DATA_IN_VALID => eoc,
  READY_TO_SEND_DATA => s_send_data_controller_READY_TO_SEND_DATA,
  ONES => ones_in,
  TENTHS => tens_in,
  HUNDERTHS => hunds_in,
  DATA_OUT => s_send_data_controller_data_out,
  SEND_DATA_TRIGGER => s_send_data_controller_SEND_DATA_TRIGGER,
  SEND_DATA_IN_UART_FLAG => s_send_data_in_uart_flag
);





U0: derivative_down 
 	 port map( CLK => s_clk_sys, D_IN => s_start_measure,
    	STROBE => strobe);

U1 : logic
port map (
	SYS_CLK => s_clk_sys,
	RST => s_rst,
	DATA_IN_VALID => eoc,
	START_MEASURE => strobe,
	DATA_IN => data_in,
	SEND_TRIGGER => trigger,
	CM => put_out,
	SEND_DATA_IN_UART_FLAG => s_send_data_in_uart_flag
	);
	
U10: bin2bcd_12bit_sync
port map( 
    binIN       => fixed_put_out,   -- this is the binary number
    ones        => ones_in,    -- this is the unity digit
    tenths      => tens_in,     -- this is the tens digit
    hunderths   => hunds_in,     -- this is the hundreds digit
    thousands   => dont_con,      -- 
    clk         => s_clk_sys                           -- clock input
);


U2 : sensor_driver
generic map (triger_pulse => C_PULSE_WIDTH, wait_time => C_WAIT_TIME,max_pulse_echo => C_MAX_PULSE_ECHO , number_of_pulses_per_cm => C_NUMBER_OF_PULSES_PER_CM)
port map (
	SYS_CLK => s_clk_sys,
	RST => s_rst,
	EOC => eoc,
	DURATION => data_in,
	TRIG_IN => trigger,
	ECHO => s_echo,
	TRIG_OUT => s_trig_out
	);

U3: to_7seg_converter
port map(
	BCD_IN => ones_in,
	D_OUT => ones_out
	);

U4: to_7seg_converter
port map(
	BCD_IN => tens_in,
	D_OUT => tens_out
	);

U5: to_7seg_converter
port map(
	BCD_IN => hunds_in,
	D_OUT => hunds_out
	);



end architecture;

Test bench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity distance_measure_sys_tb is
end entity;

architecture behave of distance_measure_sys_tb is
component distance_measure_sys is
  generic(
     C_NUMBER_OF_PULSES_PER_CM : integer:= 2915; 
     C_PULSE_WIDTH: integer:= 600; -- 600 = 12־¼ in 50MHZ clock.  
     C_WAIT_TIME: integer:= 2500000; -- 2500000 = 50m in 50MHZ clock.  
     C_MAX_PULSE_ECHO: integer:= 1800000;  -- 1800000 = 36m in 50MHZ clock.
     C_CLOCK_DIVIDER : integer:= 5209; 
     C_PARITY_ENABLE : std_logic:= '0'; -- parity_enable = '0' no parity
     C_EXTRE_STOP_BIT_ENABLE : std_logic:= '0' -- EXTRE_STOP_BIT_ENABLE = '1' use two stop bit.
    );
  port(
    CLK_SYS,RST,START_MEASURE,ECHO: in std_logic;
    TRIG_OUT,Tx_UART_OUT: out std_logic;
    -- display in cm
    LED: out std_logic;
    LED2: out std_logic;
    LED3: out std_logic;
      ONES : out std_logic_vector(6 downto 0);
      TENS : out std_logic_vector(6 downto 0);
    HUNDS : out std_logic_vector(6 downto 0)
    );
end component;

-------------constant-------------------
	constant C_CLK_PRD	: time := 20 ns; -- 20 ns = 50MHZ clock. 

-------------signals--------------------
signal s_clk,s_echo,s_rst,start_measure,trig_out		: std_logic :='0';
signal ones_out, tens_out, hunds_out             : std_logic_vector(6 downto 0);
begin

s_clk <= not s_clk after C_CLK_PRD / 2;
s_rst <= '1', '0' after 2 ns;
s_echo <= '0','1' after 500 ns, '0' after 1000 ns , '1' after 8700 ns, '0' after  13000 ns;
start_measure <= '0', '1' after 10 ns , '0' after 50 ns ,  '1' after 5000 ns , '0' after 5050 ns; 

U1: distance_measure_sys 
port map(
  CLK_SYS => s_clk,
  RST => s_rst,
  ECHO => s_echo,
  START_MEASURE => start_measure,
  TRIG_OUT => trig_out,
  ONES => ones_out,
  TENS => tens_out,
  HUNDS => hunds_out
);

end architecture;